Embodiments of the present invention relate generally to semiconductor devices, and more particularly, to semiconductor chips having superjunction cells and supporting higher breakdown voltages.
Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.
Superjunction devices, including, but not limited to metal-oxide-semiconductor field-effect transistors (MOSFET), diodes, and insulated-gate bipolar transistors (IGBT), have been or will be employed in various applications such as automobile electrical systems, power supplies, and power management applications. For example, superjunction devices may specifically be employed in light emitting diode (LED) televisions, electric or hybrid cars, LED light bulbs, servers, tablets, uninterruptable power supplies (UPS), and the like. Such devices sustain high voltages in the off-state and yield low voltages and high saturation current densities in the on-state.
FIG. 1A is a schematic top plan view of a semiconductor chip 10 having a MOSFET region 12, a gate pad region 14, and a number of gate feed regions 16 as are conventionally known. In one commercial embodiment of the chip 10, the breakdown voltage of the chip 10 is about 685 Volts (V). FIG. 1B is a schematic top plan view of a first test chip 11A, which like the main chip 10, includes a MOSFET region 12 and a gate pad region 14. However, the gate feed regions 16 have been removed from the first test chip 11A. The breakdown voltage of the first test chip is slightly higher than 685 V. In FIG. 1C, a second test chip 11B is shown with both the gate feed regions 16 and the gate pad region 14 removed. The breakdown voltage of the second test chip 11B is about 708 V.
This demonstrates that the breakdown voltage of a chip is limited by the component having the lowest breakdown voltage. In this case, the breakdown voltages of gate feed regions 16 are lower than that of the gate pad region 14, which is lower than that of the MOSFET region 12. In fact, the breakdown voltages of the main chip 10 and the first test chip 11A are always lower than the second test chip 11B by about 10-40 V.
FIG. 2 is an enlarged partial cross-sectional view of a prior art chip 10 proximate a gate feed region 16. The gate feed region 16 includes a plurality of trenches 20A, 20B formed in a semiconductor layer 22 and spaced apart from each other by about 15 micrometers (μm). First columns 24 of a first conductivity type (typically p-type) are formed extending along and adjacent to sidewalls of each of the plurality of trenches 20A, 20B. A second column 26 of a second conductivity type opposite to the first conductivity type (e.g., n-type) is disposed between respective first columns 24 bordering adjacent trenches 20A, 20B. In FIG. 2, the outer-most trenches 20A separate the gate feed region 16 from MOSFET cells 19 located in the MOSFET region 12. Thus, in this cross-sectional view, the gate feed region 16 includes at least four trenches 20A, 20B.
A deep doped region 28 of the first conductivity type extends between the two inner-most trenches 20B beneath the gate feed 30. A thick layer of oxide 32 separates the deep doped region 28 from the gate feed 30, which is coupled to a metal contact 34. Channel regions 36 of the first conductivity type are disposed above the first and second columns 24, 26 between the inner-most trenches 20B and outer-most trenches 20A. Each channel 36 includes a body contact region 38 coupled to a metal source contact 40 that connects the body contact region 38 to an adjacent MOSFET cell 19.
FIG. 3 is an enlarged partial cross-sectional view of a prior art chip 10 proximate a gate pad region 14. The structure shown in FIG. 3 is similar to that of FIG. 2. However, there are more than two “inner” trenches 20B (all spaced apart from each other by about 15 μm) disposed in the semiconductor layer 22 between the outer-most trenches 20A separating the MOSFET region 12 from the gate pad region 14. As a result, a plurality of deep doped regions 28 are present, each located beneath a respective one of a plurality of pad regions 50 and separated from the deep doped regions 28 by a thick layer of oxide 32. The pad regions 50 are all electrically connected to a gate pad contact 54.
It is desirable to equalize the breakdown voltages of the gate feed regions 16 and gate pad region 14 with the breakdown voltage of the MOSFET region 12 in order to achieve maximum capabilities from the chip 10.